In semiconductor manufacturing, silicon oxides are removed to form, for example, holes where diffusions are to be made or to allow for the deposition of interconnect materials. In other applications, holes or grooves are provided for trench capacitors.
As used in connection with the present invention, the term "silicon oxides" includes silicon dioxide (whether formed through Thermal oxidation or CVD processes), polysilicon, and doped polysilicon or other silicon oxides. One example of a doped silicon oxide is boronphosphosilicate glass (BPSG).
Current processes for etching silicon oxides typically involve The use of hydrofluoric acids (HF) or buffered HF (typically buffered with, for example, ammonium fluoride). The advantage of using HF-based wet etches in semiconductor processing is that pure silicon, which typically forms the substrate on which The silicon oxides arc found, etches at a very low rate with respect to the rates at which silicon oxides etch. As a result, the underlying silicon or, in some cases, gallium arsenide (GaAs), can serve as an etch stop to control the depth of etching on the semiconductor wafer.
In addition, etches using hydrofluoric acid can be used with pure silicon oxides or with doped silicon oxides, although etch rates may vary depending on the type and concentrations of the dopant or dopants. Although HF-based wet etching offers advantages, it also suffers from a number of disadvantages. The acids can produce severe burns if they come into direct contact with skin. Furthermore, fumes from the hydrofluoric acid can also produce skin irritation and/or eye damage in operators. Furthermore, other acids are often used in combination with HF including HNO.sub.3, H.sub.2 SO.sub.4, and others. All of these acids can cause severe burns and/or eye damage.
A further disadvantage of known wet etching processes is that they can involve the production of halides, further complicating the safety concerns during etching.
Because of the potentially dangerous nature of acids used in wet etching, expensive systems must be used to control the acids and any fumes that result from their use. This, of course, adds to the cost of semiconductor processing.
One alternative to the use of HF for etching silicon oxides is to use a hot alkaline base. Examples of two bases useful for etching silicon oxides include sodium hydroxide and potassium hydroxide. Drawbacks to using hot alkaline bases for etching are that they also etch pure silicon and gallium arsenide and they attack the organic masking materials used in many semiconductor manufacturing processes. Furthermore, many of the personnel safety concerns present when dealing with HF-based wet etching are also present when using strong bases for etching silicon oxides.
Another disadvantage for both HF-based etching and alkaline base etching is that the semiconductor wafers must be thoroughly cleaned after either process to prevent contamination of the wafer. Contamination can, of course, increase defects and waste.
Yet another process that involves removing silicon oxide from semiconductor wafers is Chemical Mechanical Polishing (CMP) (also referred to as Chemical Mechanical Planarization) which is used to planarize semiconductor wafers before further processing or to provide a layer having a known thickness. Planarization of wafers smooths the surface of the wafer to allow for more uniform layers to be formed above the layer being planarized. CMP is useful with silicon oxides formed by any process.
In general, CMP involves holding or rotating a wafer of semiconductor material against a wetted polishing surface under controlled chemical slurry, pressure and temperature conditions. The chemical slurry may contain abrasive agents and/or chemical etchants. The chemical etchants can include bases and catechols as a complexing agent to chemically remove silicon oxides.
Disadvantages of known CMP processes include that the bases used to chemically etch the silicon oxides pose the safety concerns discussed above. Furthermore, the bases and any abrasive agents also pose contamination problems if the wafer surface is not thoroughly cleaned after the CMP process is finished.